This invention relates to the field of multilayer capacitor elements, and more particularly, to a multi-chip module having an integral multilayer capacitor element formed in the module substrate.
Analog signal processor modules (ASPM) typically connect to an analog video substrate. The analog signal processor module requires low cross-talk between 20 MHZ analog signals, high (44 MHZ) and low speed clock line interconnections, and power and ground connections. Typically, as shown in the prior art of FIG. 1, the capacitors associated with this type of prior art interconnection are placed several inches away from the bond pad because of the straight mechanical layout and configuration requirements, as well as design limitations associated with this type of module. Because the capacitors are so remote from a bond pad, and typically formed as a discrete component, they are less effective in performing their desired functions. These capacitors also take up valuable substrate real estate that could be used for active components, as well as make reduction in current module size difficult.
As shown in prior art FIG. 1, an analog signal processor module includes a capacitor and a focal plane array (FPA) structure. The components are surface mounted on the analog signal processor module and a CCD substrate positioned on the focal plane structure. These type of applications are used with phased array antenna transmit/receive modules and typically include low temperature co-fired ceramic (LTCC) circuit applications.
Other applications attempt to overcome the drawback of using discrete components, and instead use conventional buried capacitor structures or xe2x80x9cplanarxe2x80x9d capacitors such as used in traditional multi-chip module interconnections. In order to place bond pads closer to some of these capacitors, substrates have been designed to allow edge metallization by exposing solid internal vias formed in the ceramic. These types of structures typically have used discrete captive elements. The capacitor positioning problem also has not been solved with these systems.
It is therefore an object of the present invention to provide a multi-chip module substrate using an edge bond with an integral capacitive element in or near the bond pad to provide coupling/decoupling, filtering or DC blocking capacitive structures.
It is still another object of the present invention to provide an embedded capacitor structure in a multi-chip module that includes an edge coupled point of contact for the module.
In accordance with the present invention, a multi-chip module has an integral capacitor element and includes a plurality of substrate layers forming a multi-chip module substrate. At least one via is formed in the substrate. A conductive material fills a portion of the via and a dielectric capacitive material fills the via for a plurality of substrate layers and engages the conductive material within the via to define a multilayer capacitor. The substrate has a cut edge that extends through at least a portion of the via for exposing the conductive material that fills the via to define a bondable edge.
In one aspect of the present invention, the cut edge extends through the via off-center to aid in retaining the conductive material within the via. The cut edge extends through the capacitive material to form an exposed edge of the capacitive material. A cap structure can be positioned on the exposed edge of the capacitive material.
In still another aspect of the present invention, the conductive material fills the via around the capacitive material. A signal trace can be formed on one of the substrate layers and engages the conductive material within the via. The conductive material filling the via can preferably comprise a gold and glass binder. In still another aspect of the present invention, the layers are formed from ceramic. A ground line can also be formed on one of the layers to engage the capacitive material.
In still another aspect of the present invention, the capacitive material comprises a high K dielectric material. The high K dielectric material has about a 10,000 to about 20,000 K dielectric. The high K dielectric, in still another aspect, can have about a 100,000 to about 200,000 K dielectric. The cut edge defining the bondable edge can be about eight mil square.
In still another aspect of the present invention, the multi-chip module has an integral capacitor element. A plurality of substrate layers form a multi-chip module substrate and the formed substrate has a cut edge. A via is formed in the substrate adjacent to the cut edge. A dielectric capacitive material fills the via for a plurality of substrate layers and defines a multilayer capacitor. Means is formed on the cut edge and defines a bondable edge. Means electrically interconnects the bondable edge and capacitive material and means connects at least two layers of the dielectric capacitive material.
In yet another aspect of the present invention, the means connecting at least two layers of the dielectric capacitive material comprises a conductive via. The capacitor defines an upper and lower portion within the via. A signal trace is formed on a substrate layer and is connected to one of either upper or lower portions of the capacitor to form a DC blocking capacitor structure. A ground line can also be formed on one of the substrate layers and connected to one of either upper or lower portions of the capacitor, while a signal trace can be formed on one of the substrate layers to engage the bondable edge to define a decoupling capacitor structure.
A post-fired bond pad can be formed on the bondable edge. However, in accordance with a preferred aspect of the present invention, the means formed on the cut edge and defining a bondable edge comprises a solid conductive via that has been cut to expose the solid conductive material forming the conductive via. The solid conductive via has preferably been cut off-center to aid in retaining the conductive material within the cut conductive via.
In a method aspect of the present invention, the method comprises the step of forming a multi-chip module having an integral capacitor element and comprises the steps of forming a plurality of substrate layers to form a multi-chip module substrate. The method further comprises forming a via within the substrate and filling the via with a dielectric capacitive material for a plurality of substrate layers to define a multilayer capacitor. The method further comprises the step of cutting the substrate to form a bonding surface that engages the dielectric capacitive material.
In accordance with the present method of the invention, the method further comprises the step of positioning the via having the dielectric capacitive material at the cut edge and including the step of filling at least a portion of the via with a conductive material to form the bondable surface. The method also comprises the step of forming a signal trace on one of the substrate layers and interconnecting the capacitor to form a DC blocking capacitor structure. The method also comprises the step of forming a ground line on one of the substrate layers and interconnecting the capacitor with the ground line. The method further comprises the step of forming a signal trace on one of the layers and engaging the bondable edge to define a decoupling capacitor structure. The method further comprises the step of forming a post-fired bond pad at the bondable edge. The method further comprises the step of forming a conductive via that has been cut to expose the conductive material to define the bondable edge.
The via is preferably formed off-center to aid in retaining the conductive material within the via. The capacitive material can be formed to form an exposed edge of the capacitive material, which can include a cap structure on the exposed edge. The via is preferably filled with a gold and glass binder.